As annotation i also already tried:
-connecting the output with an input pin, and use that with a flipflop signal as trigger: always change the output signal, when the input signal changes. this leads to flipflop signals with ~7.5ms each. So 3x cycle time
-the python library RevPiModIO: the minimum ...
Search found 2 matches
- 18 Aug 2021, 14:42
- Forum: Software
- Topic: Signal modulation with max cycle time
- Replies: 1
- Views: 1656
- 18 Aug 2021, 14:27
- Forum: Software
- Topic: Signal modulation with max cycle time
- Replies: 1
- Views: 1656
Signal modulation with max cycle time
Dear folks,
i want to modulate a signal with the maximum cycle time of the dio bridge, around ~2.5ms. (RevPiIOCycle is 2, cropped integer value)
ATM im counting the RTC ticks in a main while loop, but hence its not synchronized, there is a periodical gap, where my output signal is one cylce longer ...
i want to modulate a signal with the maximum cycle time of the dio bridge, around ~2.5ms. (RevPiIOCycle is 2, cropped integer value)
ATM im counting the RTC ticks in a main while loop, but hence its not synchronized, there is a periodical gap, where my output signal is one cylce longer ...